# 華為目標於2031年達成1.4奈米晶片效能。

*semiconductor · news · 2026-05-26 · Caixin*

## Key points

- 華為推出Tau (τ) 縮放定律以推動晶片效能進步。
- 公司目標於2031年達成1.4奈米晶片效能，無需依賴先進製程。
- 華為新開發的LogicFolding技術在麒麟處理器中垂直堆疊數位、類比及記憶體電路。
- 此方法最小化晶片層間的訊號傳輸時間，提高舊製程節點的效率。

Huawei targets 1.4-nanometer chip performance by 2031 Huawei Technologies Co. Ltd. expects to match the performance of industry-leading 1.4-nanometer chips by 2031 using a novel design architecture, signaling a major step in bypassing U.S. curbs on its access to advanced manufacturing tools. He Tingbo, president of the company’s semiconductor division, unveiled the Tau (τ) Scaling Law at an international symposium on Monday. The new theoretical framework focuses on minimizing signal transmission time across vertically stacked chip layers rather than shrinking the physical size of transistors. Under the new approach, Huawei’s upcoming Kirin processors, due this autumn, will feature “LogicFolding” technology. By vertically stacking digital, analog, and memory circuits, the method shortens transmission paths and reduces resistance, allowing chips to operate more efficiently on older manufacturing nodes.

**Companies:** Huawei Technologies Co. Ltd.
**Countries:** China

[Read the full story on Caixin](https://www.caixinglobal.com/2026-05-26/tech-brief-may-26-huawei-targets-14-nanometer-chip-performance-by-2031-with-new-design-architecture-102447554.html)

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