# 台積電看到客戶優先追求更低功耗的效能提升。

*semiconductor, genai · news · 2026-05-28 · The Economic Times*

## Key points

- 台積電表示，AI 飆升的電力需求現已成為晶片開發的主要限制。
- 台積電計劃其 A14 晶片世代相較於 N2 製程降低最多 30% 的功耗。
- 從智慧型手機到資料中心的客戶，現在優先考量能源效率勝過純計算效能。
- 台積電延後採用 ASML 下一代極紫外光（EUV）光刻技術，專注於節能設計特性。

Synopsis AI's massive electricity needs are now driving chip development. Energy efficiency is becoming more critical than raw computing power. TSMC, a leading chipmaker, sees customers prioritizing performance gains that use less power. This shift impacts smartphones to AI data centers. New technologies like advanced packaging and chip stacking are key. TSMC aims for significant power reduction in upcoming chip generations. Listen to this article in summarized format A senior TSMC executive said on Thursday that surging electricity demands from AI are making energy efficiency rather than computing power the main constraint shaping future computer chip development. Kevin Zhang, Senior Vice President of Business Development, said customers across smartphones to AI data centres are increasingly prioritising performance gains that do not drive up power use, as operators contend with ‌the cost ⁠and availability ⁠of electricity. "The area customers most want improvement in is energy efficiency. This is true across the board, ​whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center," Zhang ​told reporters at a conference in Amsterdam. The shift is part of a broader turning point for the semiconductor industry, where simply packing more transistors onto chips is no longer ​enough to sustain performance gains for energy-hungry AI workloads. TSMC, ⁠the world's ‌largest contract chipmaker, makes AI chips for Nvidia and AMD, as well as custom AI processors for major cloud companies including Google, Amazon, Meta ⁠and Microsoft. Zhang said improvements in transistor density remain central to ​TSMC's roadmap, but other approaches - such as advanced packaging, chip ​stacking and photonics - are becoming increasingly important to boost efficiency. He said TSMC expects its chips to cut power consumption by up to 30% between its current N2 technology and its A14 generation, due around 2028, while delivering more than 20% higher computing performance. The comments come as rivals also explore alternative ways to keep improving chip performance. Chinese competitor ‌Huawei unveiled its 'Tau Scaling Law' plan this week to improve performance by speeding up data movement within chips. "The concept has been around in ​this industry for ​long enough," Zhang said, ⁠describing it as largely dependent on integrating components more closely, such as through 3D stacking. Huawei's approach reflects constraints facing Chinese firms, which are barred by U.S.-led export controls from ​accessing extreme ultraviolet (EUV) lithography machines made by Dutch ASML - advanced tools for printing smaller circuits. TSMC, a major buyer of ASML's EUV systems, said in April it would delay adoption for several years of the next generation of the technology, highlighting how design features improving energy efficiency are becoming more urgent than smaller circuitry for its coming generation of AI chips. (Catch all the Technology News News, and Latest News Updates on The Economic Times.) ...more

**Companies:** TSMC, Nvidia, AMD, Google, Amazon, Meta, Microsoft
**Countries:** China, Netherlands, United States, Taiwan

[Read the full story on The Economic Times](https://economictimes.indiatimes.com/tech/artificial-intelligence/energy-use-forcing-rethink-of-ai-chip-design-tsmc-says/articleshow/131374309.cms)

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