Intel's upcoming Diamond Rapids Xeon will boost core counts to 192, a 50 percent increase over last generation.

COMPUTEX 2026 Intel’s upcoming Diamond Rapids Xeon will boost core counts to 192, a 50 percent increase over last generation, the x86 giant revealed at Computex in Taipei this week. But while core counts continue to rise, in doing so Intel has managed to cut thread counts by a quarter. Yep, Hyperthreading – Intel's marketing for simultaneous multithreading – is officially dead. REG AD Intel first added support for SMT all the way back in 2002. The technology boosted utilization by enabling two threads to harness idle execution units during a single cycle. While SMT doesn’t double throughput, for certain applications it can deliver double-digit percentage gains. REG AD After slowly abandoning the tech across its consumer product lineup, Intel's Xeons are latest to get the cut. Except, wait! It seems Intel may have seen the error of its ways, and is already reversing course on the decision. Intel’s next next Xeon, codenamed Coral Rapids, will bring SMT back. The jump from 128 to 192 is a big jump for Intel, but still smaller than the AMD is making with its 256-core Venice Epycs. If that weren’t enough, it looks like AMD could beat Intel to market by as much as a year. Diamond Rapids is now slated for release sometime in 2027. Echos of Epyc, notes of Monaka In addition to core count, we also got our first look at how Intel will stitch the chip together. It turns out AMD might have been onto something when it started gluing silicon together back in 2017, because Intel’s next round Xeons look more like an Epyc under the hood than ever. We know the chip will be fabbed using Intel’s 18A-P process tech, a refined version of its 2nm-class process tech. Beyond this details get a little fuzzy. From the renders shared in Intel’s press deck, we can see what appear to be two I/O dies serving four vertically stacked compute assemblies assembled using its Foveros packaging tech. REG AD This isn’t the first time we’ve seen something like this from Intel. Intel’s Clearwater Forest, which is finally launching after years of teasing, also used a similar arrangement, with four 24-core compute tiles sitting atop a base die containing the memory controller and L3 cache. Moving the L3 cache to the base die frees up a lot of die area on the compute chiplet. In this case, we're looking at four 48-core compute chiplets. In this respect, Diamond Rapids looks a lot like another CPU we’ve looked at recently: Fujitsu’s Monaka. That chip uses an almost identical chip layout, albeit with one I/O die rather than two. While we’re fairly certain Diamond Rapid’s L3 cache will live on the base die, the memory controller could be housed on the four base dies or it could be on the I/O dies, similar to what AMD has done since Rome launched in 2019. If we had to guess, our bet would be on the I/O die, since it would reduce the number of NUMA nodes to one or two as opposed to four. Not a mainstream part Unlike Intel’s last P-core Xeon, codenamed Granite Rapids, don’t expect to see Diamond Rapids deployed widely in enterprise virtualization or storage servers. According to Intel, Diamond Rapids is “optimized for high-demand IaaS, high-perf/thread,” putting it in the same class as its high-performance-computing (HPC)-centric 6900P-series parts. REG AD The lack of SMT complicates hypervisor licensing models. Where you once got two threads for the price of one, Diamond Rapids customers will now be getting half as many for their dollar. There are of course ways of getting around this. Oracle rented out its Ampere-based instances, which also lack SMT, in core-pairs rather than on a core-per-core basis, but something like this would presumably require buy-in from the likes of VMware or RedHat. As with past HP- optimized processors, Diamond Rapids will be packing a much beefier memory bus than most folks are going to be looking for. HPC workloads like their memory bandwidth and the next-gen Xeon will have no shortage of it with 16-channels of DDR5. Intel hasn’t disclosed what memory speeds the chip will support out of the box. With that said, Clearwater is already at 8000 MT/s on standard RDIMMS, and Granite could hit 8800 MT/s on MRDIMMS — in fact, 9600 MT/s DIMMS wouldn’t be an unreasonable assumption. That works out to 1.2 TB/s of bandwidth per socket, which happens to be the same as Nvidia’s LPDDR5X-packed Vera CPUs. That’s not the only thing we're still in the dark about. Power consumption and instruction per clock gains from the chip’s new architecture are details we expect Intel to trickle out. The good news: we won’t have to wait long for the next round of specifications, as Intel will be presenting on Diamond Rapids at Hot Chips in August.

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