semiconductor / news / / International Business Times
Huawei says it has developed a new chip design approach it claims could help it achieve cutting-edge semiconductor performance within five years.
Huawei unveiled a 'LogicFolding' design using vertically stacked chip layers to bypass EUV lithography limits.
KEY POINTS
- The company introduced the 'Tau Scaling Law' to reduce data travel time in 3D chip architectures.
- Huawei aims for Kirin processors with 1.4-nanometer-class transistor density by 2031, matching global leaders’ targets.
- This approach seeks to sidestep US export controls that restrict access to advanced lithography equipment.
COMPANIES
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